In-circuit testing of printed circuit boards is a technology at least 25 years old. In-circuit tests look for manufacturing faults, as opposed to defects of the integrated circuits, that may occur during the assembly of the board. The in-circuit test presumes that the integrated circuits, or devices, are good as a result of earlier device testing and focuses on the quality of the manufacturing process by testing each device to ensure that it is placed and soldered correctly. As a by-product of this testing, the device logic is tested by checking input/output receivers and drivers for possible damage that may have occurred while the devices and board were handled during the manufacturing process.
In the simplest case of testing devices, a standalone device is tested by surrounding it with probes and applying digital inputs in order to observe digital outputs. If two or more devices are attached together, the in-circuit test will require probe contact with each node (i.e., where two or more pins converge). Each device is tested by stimulating all inputs and causing all outputs to change at least once. The goal is that if there is a failure at any input, that failure will propagate through the device so that an output will eventually respond incorrectly. The data used to test an individual device is referred to as predefined tests which can be used by an in-circuit tester.
Pre-defined tests are often not comprehensive enough to account for the different topological constraints that might occur on a complex circuit board. For example, where two devices are being tested and the output on a first device shares the same node as an input on a second device, testing the second device would entail overdriving competing outputs from the first, or upstream, device. While in-circuit testers have sufficient overdrive capability to win when establishing input states, it is possible for the upstream device to suffer damage due to this overdrive on its outputs. If this is a concern, the Pre-defined test may need to be augmented to condition the outputs of the upstream device such that damage is avoided. Similarly, a pre-defined test may need to be augmented where two devices have one of their output pins tied together so that if the first device is tested, the output on its pin may not be readable if the second device's output pin is enabled. As another example, a device can have an input tied directly to a fixed voltage such that the pin cannot be stimulated with data. This could rule out a pre-defined test for this device that was created with the assumption that the pin was free to move. A tied pin constraint can also occur where a device has two input pins tied to the same node. If a pre-defined test for such a device required different states to be applied to the pins at any one time, then the constraint would not allow the test to be applied.
In-circuit testers have dealt with these problems for many years. One solution has been to include an in-circuit program generator (hereinafter referred to as an IPG) in the test system that analyzes board interconnect topology and then attempts to build executable tests from an externally supplied digital library of pre-defined information and tests. These libraries are called digital libraries, and are manually created by engineers. The tests can either be written at the board level such that they are tailored to the device configuration on the board, or the tests can be written without knowledge of board configuration such that they anticipate different configurations of the board. This process of manually creating tests, however, is time-consuming, resource-consuming, and very expensive. Talented engineers may spend weeks analyzing a device, writing the tests, and then verifying them. As a result, the tests are often incomplete or of marginal quality. For example, disable methods for a device may be missing for some outputs, or the device may only have a presence and orientation test available. Additionally, if the tests are written at the board level, they are often written for a device configuration that is subsequently modified. As a result, the tests become outdated and need to be redesigned. Another solution is to use a library creation service provider to create digital library tests. However, these providers often only accept orders for widely used devices so that they can spread the cost over many users. As a result, service providers cannot handle the increasingly growing number of custom, one-of-a-kind devices.
While digital library tests can provide an IPG with the information necessary to create executable tests that consider the topological constraints of the board, they are time and labor intensive, expensive, and have the potential to be outdated very quickly. As a result, there is a need for a method and an apparatus of developing digital libraries to:
reduce the time and expense of creating device tests; PA1 maximize the amount of information and tests that can be provided about a device; PA1 increase the accuracy and reliability of device information; and PA1 increase the probability that useful tests survive board level constraints.